IGBTs are widely used in high-voltage power electronic systems such as variable-frequency drives and inverters. It is desirable that there is a low power loss in the device. Conduction loss of an IGBT is a major component of the power loss, and the conduction loss is characterized by the on-state voltage drop of the device. Therefore, an objective of the present invention is to provide an IGBT having the theoretically lowest on-state voltage drop.
FIG. 1 shows a cross section of an IGBT device 100 as the prior art. The device 100 is a MOS-controlled PNP bipolar junction transistor. The MOS channel includes an n+ emitter region (112), a p-type base region (113), an n− drift region (114), a gate dielectric (130) and a gate electrode (121). The p-type base region (113) is connected to an emitter electrode (120) through a p+ diffusion region (111). The MOS channel controls the on-state and off-state of the device. At the on-state of the device 100, holes are injected from the p+ collector region (116)/n-type buffer region (115) junction at the back surface. In addition, electrons are conducted by means of the MOS channel, and the non-equilibrium electrons and holes form high-concentration plasma in the lightly doped n− drift region (114), so that high conductivity is obtained in the n− drift region (114). However, because of the slightly reverse biased junction of the n− drift region (114) and p-type base region (113), the concentration of electron-hole plasma near the junction is relatively low. FIG. 2 shows the concentration of electron-hole plasma as a function of the distance in the n− drift region (114). As shown in the figure, because of the drift current at the junction of the n− drift region (114) and the p-type base region (113), the concentration of the electron-hole plasma there is almost zero. Because of the reduced concentration, the on-state voltage drop of the device 100 is larger than the on-state voltage drop of a p-i-n diode. If the slightly reverse biased junction of the n− drift region (114) and p-type base region (113) can be removed, the theoretically lowest on-state voltage drop of the device 100 can be the same as the on-state voltage drop of a p-i-n diode. In the device 100, to achieve the theoretically lowest on-state voltage drop, the width of the silicon mesa between trenches needs to be reduced. When the width of the mesa is approximately 20 nm, two adjacent inversion layers will merge. When the p-type base region (113) is completely converted to an n+ inversion layer, the on-state voltage drop of the device can be the same as the on-state voltage drop of a p-i-n diode. However, actually, it is very difficult to fabricate a mesa having a width of approximately 20 nm in the device 100.